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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev.? a 08/16/2011 copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is62wv12816dall/dbll is65wv12816dall/dbll ? 128k?x?16? low? voltage, ? ultra ? low? power?cmos? static?ram ? ? ?????? ????? features ? high-speed access time: 35ns, 45ns, 55ns ? cmos low power operation C 36 mw (typical) operating C 9 w (typical) cmos standby ? ttl compatible interface levels ? single power supply C 1.8v 10% v dd (is62/65wv12816d all) C 2.5v--3.6v v dd (is62/65wv12816dbll) ? fully static operation: no clock or refresh required ? three state outputs ? data control for upper and lower bytes ? industrial and autotmovie temperature support ? 2cs option available ? lead-free available description the issi is62/65wv12816dall/dbll are high-speed, 2m bit static rams organized as 128k words by 16 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected) or when cs1 is low , cs2 is high and both lb and ub are high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. a data byte allows upper byte (ub) and lower byte (lb) access. the is62/65wv12816dall/dbll are packaged in the jedec standard 48-pin mini bga (6mm x 8mm) and 44- pin tsop (type ii). functional?block? diagram september?2011 a0-a16 cs1 oe we 128k x 16 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb cs2
is62wv12816dall/dbll, is65wv12816dall/dbll ? 2 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ? rev.? a 08/16/2011 pin? configurations 48-pin?mini?bga?(6mm?x?8mm) (package ?code?b) pin?descriptions a0-a16 address inputs i/o0-i/o15 data inputs/outputs cs1, cs2 chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 cs1 i/o0 i/o1 i/o2 i/o3 vdd gnd i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd vdd i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 nc 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 n/c i/o 8 ub a3 a4 csi i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 nc a7 i/o 3 v dd v dd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc 48-pin?mini?bga?(6mm?x?8mm) 2?cs?option? (package?code?b2) 44-pin?mini? tsop? (type?ii) (package ?code? t) 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 cs2 i/o 8 ub a3 a4 cs1 i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 nc a7 i/o 3 vdd vdd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc
integrated silicon solution, inc. www.issi.com 1-800-379-4774 3 rev.? a 08/16/2011 is62wv12816dall/dbll, is65wv12816dall/dbll ? truth ? table ? ? ? ? ? ? ? i/o?pin ? mode? we? cs1? cs2? oe? lb ub? i/o0-i/o7? i/o8-i/o15? v dd ?current? ? not selected x h x x x x high-z high-z i sb 1 , i sb 2 x x l x x x high-z high-z i sb 1 , i sb 2 x x x x h h high-z high-z i sb 1 , i sb 2 output disabled h l h h l x high-z high-z i cc h l h h x l high-z high-z i cc read h l h l l h d out high-z i cc h l h l h l high-z d out h l h l l l d out d out write l l h x l h d in high-z i cc l l h x h l high-z d in l l h x l l d in d in operating ?range?(v dd ) ? range ? ambient? temperature ? is62wv12816dall is62wv12816dbll ? commercial 0c to +70c 1.8v 10% 2.5v - 3.6v ? industrial C40c to +85c 1.8v 10% 2.5v - 3.6v is65wv12816dall is65wv12816dbll automotive -40c to +125c 1.8v 10% 2.5v - 3.6v absolute?maximum? ratings (1) ? symbol? parameter ? value ? unit ? v term terminal voltage with respect to gnd C0.2 to v dd +0.3 v t stg storage temperature C65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
is62wv12816dall/dbll, is65wv12816dall/dbll ? 4 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ? rev.? a 08/16/2011 capacitance (1) ? symbol? parameter ? conditions? max. ? unit ? c in input capacitance v in = 0v 8 pf c out input/output capacitance v out = 0v 10 pf note: 1. tested initially and after any design or process changes that may affect these parameters. dc?electrical? characteristics (over operating range) ? symbol? parameter ? test ?conditions? v dd ? min. ? max. ? unit ? v oh output high voltage i oh = -0.1 ma 1.8v 10% 1.4 v i oh = -1 ma 2.5-3.6v 2.2 v v ol output low voltage i ol = 0.1 ma 1.8v 10% 0.2 v i ol = 2.1 ma 2.5-3.6v 0.4 v v ih input high voltage 1.8v 10% 1.4 v dd + 0.2 v 2.5-3.6v 2.2 v dd + 0.3 v v il input low voltage 1.8v 10% C0.2 0.4 v 2.5-3.6v C0.2 0.6 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a notes: for is62/65wv12816dall: v il ( min.) = -1.0v a c (pluse width < 10ns). not 100% tested. v ih ( max.) = v dd + 1.0v a c ; ( pluse width < 10ns). not 100% tested. for is62/65wv12816dbll: v il ( min.) = -2.0v a c (pluse width < 10ns). not 100% tested. v ih ( max.) = v dd + 2.0v a c ; ( pluse width < 10ns). not 100% tested.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 5 rev.? a 08/16/2011 is62wv12816dall/dbll, is65wv12816dall/dbll ? is62/65wv12816dall, ??? power? supply? characteristics (1) ? (over operating range) symbol? parameter ? test ?conditions? ? ? ? ? max. ? unit ? ? ? ? ? ? ? ? 55 i cc v dd dynamic operating v dd = max., com. 15 ma supply current i out = 0 ma, f = f max ind. 20 auto. 25 i cc 1 operating supply v dd = max., com. 3 ma current i out = 0 ma, f = 0 ind. 3 auto. 4 i sb 1 ttl standby current v dd = max., com. 0.3 ma (ttl inputs) v in = v ih or v il ind. 0.3 cs1 = v ih , cs2 = v il , a uto . 0.5 f = 1 mh z or ulb control v dd = max., v in = v ih or v il cs1 = v il , f = 0, ub = v ih , lb = v ih i sb 2 cmos standby v dd = max., com. 4 a current (cmos inputs) cs1 v dd C 0.2v, ind. 6 cs2 0.2v, auto. 15 v in v dd C 0.2v, or v in 0.2v, f = 0 or ulb control v dd = max., cs1 = v il , cs2=v ih v in 0.2v, f = 0; ub / lb = v dd C 0.2v is62/65wv12816dbll, ??? power? supply? characteristics (1) ? (over operating range) symbol? parameter ? test ?conditions? ? ? max? max. ? max. ? ? unit ? ? ? ? ? ? 35? 45? 55? i cc v dd dynamic operating v dd = max., com. 22 20 18 ma supply current i out = 0 ma, f = f max ind. 23 21 19 auto. 35 30 25 typ. (2) 15 12 10 i cc 1 operating supply v dd = max., com. 3 3 3 ma current i out = 0 ma, f = 0 ind. 3 3 3 auto. 4 4 4 i sb 1 ttl standby current v dd = max., com. 0.1 0.1 0.1 ma (ttl inputs) v in = v ih or v il ind. 0.1 0.1 0.1 cs1 = v ih , cs2 = v il , a uto . 0.2 0.2 0.2 f = 1 mh z ? ? ? or? ulb control v dd = max., v in = v ih or v il cs1 = v il , f = 0, ub = v ih , lb = v ih i sb 2 cmos standby v dd = max., com. 5 5 5 a current (cmos inputs) cs1 v dd C 0.2v, ind. 7 7 7 cs2 0.2v, auto. 15 15 15 v in v dd C 0.2v, or typ. (2) 2 2 2 v in 0.2v, f = 0 ? ? ? or? ulb control v dd = max., cs1 = v il , cs2=v ih v in 0.2v, f = 0; ub / lb = v dd C 0.2v note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested.
is62wv12816dall/dbll, is65wv12816dall/dbll ? 6 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ? rev.? a 08/16/2011 ac ? test?conditions ? parameter ? is62/65wv12816dall ? is62/65wv12816dbll ? ? ? ? (unit)? (unit) ? input pulse level 0.4v to v dd -0.2v 0.4v to v dd -0.3v input rise and fall times 1v/1ns 1v/1ns input and output timing v ref v ref and reference level output load see figures 1 and 2 see figures 1 and 2 ac ? test? loads figure?1 figure?2 ? ? 1.8v??10%?? 2.5v?-?3.6v ? r1(?) 3070 3070 ? r2(?) 3150 3150 v ref 0.9v 1.5v v tm 1.8v 2.8v r1 5 pf including jig and scope r2 output vtm r1 30 pf including jig and scope r2 output vtm
integrated silicon solution, inc. www.issi.com 1-800-379-4774 7 rev.? a 08/16/2011 is62wv12816dall/dbll, is65wv12816dall/dbll ? read?cycle?switching? characteristics (1) ? (over operating range) ? 35?ns? 45?ns? 55?ns? ? symbol? parameter ? min. ? max. ? min. ? max. ? min. ? max. ? unit t rc read cycle time 35 45 55 ns t aa address access time 35 45 55 ns t oha output hold time 10 10 10 ns t a cs 1/ t a cs 2 cs1/cs2 access time 35 45 55 ns t doe oe access time 15 20 25 ns t hzoe (2) oe to high-z output 10 15 20 ns t lzoe (2) oe to low-z output 5 5 5 ns t hzcs 1/ t hzcs 2 (2) cs1/cs2 to high-z output 0 10 0 15 0 20 ns t lzcs 1/ t lzcs 2 (2) cs1/cs2 to low-z output 10 10 10 ns t ba lb, ub access time 35 45 55 ns t hzb lb, ub to high-z output 0 10 0 15 0 20 ns t lzb lb, ub to low-z output 0 0 0 ns notes: 1. test conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
is62wv12816dall/dbll, is65wv12816dall/dbll ? 8 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ? rev.? a 08/16/2011 data valid previous data valid t aa t oha t oha t rc d out address ac ? waveforms read?cycle? no. ?1 (1,2)? (address controlled) (cs1 = oe = v il , cs2 = we = v ih , ub or lb = v il ) t rc t oha t aa t doe t lzoe t ace1/ t ace2 t lzce1/ t lzce2 t hzoe high-z data valid t hzcs1/ t hzcs2 address oe cs1 cs2 dout lb , ub t hzb t ba t lzb ac ? waveforms read?cycle? no. ?2 (1,3) ( cs1, cs2, oe, and ub/lb controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, cs1, ub, or lb = v il . cs2= we =v ih . 3. address is valid prior to or coincident with cs1 low transition.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 9 rev.? a 08/16/2011 is62wv12816dall/dbll, is65wv12816dall/dbll ? write?cycle?switching? characteristics (1,2) (over operating range) ? 35?ns? 45?ns? 55?ns ? symbol? parameter ? ??min. ? max. ?? min. ? max. ? ?? min. ? max. ? ?? unit t wc write cycle time 35 45 55 ns t scs 1/ t scs 2 cs1/cs2 to write end 25 35 45 ns t aw address setup time to write end 25 35 45 ns t ha address hold from write end 0 0 0 ns t sa address setup time 0 0 0 ns t pwb lb, ub valid to end of write 30 35 45 ns t pwe we pulse width 30 35 40 ns t sd data setup to write end 15 20 25 ns t hd data hold from write end 0 0 0 ns t hzwe (3) we low to high-z output 20 20 20 ns t lzwe (3) we high to low-z output 5 5 5 ns notes: 1. test conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. the internal write time is defned by the overlap of cs1 low, cs2 high and ub or lb, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
is62wv12816dall/dbll, is65wv12816dall/dbll ? 10 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ? rev.? a 08/16/2011 ac ? waveforms write?cycle? no. ?1 (1,2) ? (cs1 controlled, oe = high or low) data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din lb, ub t pwb notes: 1. write is an internally generated signal asserted during an overlap of the low states on the cs1 , cs2 and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = (cs1) [ (lb) = (ub) ] (we).
integrated silicon solution, inc. www.issi.com 1-800-379-4774 11 rev.? a 08/16/2011 is62wv12816dall/dbll, is65wv12816dall/dbll ? data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din ac ? waveforms write?cycle? no. ?2? (we controlled: oe is high during write cycle)
is62wv12816dall/dbll, is65wv12816dall/dbll ? 12 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ? rev.? a 08/16/2011 data-in vali d data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we lb, ub dout din ac ? waveforms write?cycle? no. ?3? (we controlled: oe is low during write cycle)
integrated silicon solution, inc. www.issi.com 1-800-379-4774 13 rev.? a 08/16/2011 is62wv12816dall/dbll, is65wv12816dall/dbll ? data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 t hd t sa t hzwe address cs1 ub, lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha ub_cswr4.eps high cs2 ac ? waveforms write?cycle? no. ?4? (ub/lb controlled)
is62wv12816dall/dbll, is65wv12816dall/dbll ? 14 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ? rev.? a 08/16/2011 data ?retention? waveform ? (cs1 controlled) data ?retention?switching? characteristics ? ? symbol? parameter ? test ?condition? ? min. ? max. ? unit v dr v dd for data retention see data retention waveform 1.5 3.6 v i dr data retention current v dd = 1.5v, com. 4 a cs1 v dd C 0.2v, ind. 6 a cs2 v dd C 0.2v, or auto. 15 a 0v cs2 0.2v, 0v vin typ. (2) 2 a t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns data ?retention? waveform ? (cs2 controlled) vdd cs1 vdd - 0.2v t sdr t rdr v dr cs1 gnd data retention mode cs2 0.2v t sdr t rdr v dr cs2 gnd data retention mode vdd note: 1. in data retention mode, cs2 controls the address, we, cs1, oe, and the din buffer. if cs2 controls data retention mode, vin (for these inputs) can be in the high impedance state. if cs1 controls the data retention mode, cs2 must satisfy either cs2 vcc C 0.2 v or cs2 0.2 v. the other input levels (address, we, oe, i/o) can be in the high impedance state. 2. typical values are measured at v dd = v dr (min), t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 1-800-379-4774 15 rev.? a 08/16/2011 is62wv12816dall/dbll, is65wv12816dall/dbll ? ordering? information: ? is62wv12816dall?(1.65v?-?2.2v) industrial? range: ?C40c?to?+85c ? speed?(ns)? order ? part?no. ? packag e 55 is62wv12816dall-55ti tsop (type ii) is62wv12816dall-55bi mini bga (6mm x 8mm) is62wv12816dall-55bli mini bga (6mm x 8mm), lead-free is62wv12816dall-55b2i mini bga (6mm x 8mm), 2 cs option ordering? information: ?is62wv12816dbll?(2.5v?-?3.6v) industrial? range: ?C40c?to?+85c ? speed?(ns)? order ? part?no. ? pac kage 35 is62wv12816dbll-35tli tsop (type ii), lead-free is62wv12816dbll-35bli mini bga (6mm x 8mm), lead-free is62wv12816dbll-35b2li mini bga (6mm x 8mm), 2 cs option, lead-free 45 is62wv12816dbll-45tli tsop (type ii), lead-free is62wv12816dbll-45bli mini bga (6mm x 8mm), lead-free is62wv12816dbll-45b2li mini bga (6mm x 8mm), 2 cs option, lead-free 55 is62wv12816dbll-55ti tsop (type ii) is62wv12816dbll-55tli tsop (type ii), lead-free is62wv12816dbll-55bi mini bga (6mm x 8mm) is62wv12816dbll-55bli mini bga (6mm x 8mm), lead-free is62wv12816dbll-55b2i mini bga (6mm x 8mm), 2 cs option is62wv12816dbll-55b2li mini bga (6mm x 8mm), 2 cs option, lead-free ordering? information: ?is65wv12816dbll?(2.5v?-?3.6v) automotive ? range?(a3): ?C40c?to?+125c ? speed?(ns)? order ? part?no. ? pac kage 45 is65wv12816dbll-45tla3 tsop (type ii), lead-free is65wv12816dbll-45bla3 mini bga (6mm x 8mm), lead-free
is62wv12816dall/dbll, is65wv12816dall/dbll ? 16 integrated silicon solution, inc. www.issi.com 1-800-379-4774 ? rev.? a 08/16/2011 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/12/2008 package outline
integrated silicon solution, inc. www.issi.com 1-800-379-4774 17 rev.? a 08/16/2011 is62wv12816dall/dbll, is65wv12816dall/dbll ? 2. dimension d and e1 do not include mold protrusion . 3. dimension b does not include dambar protrusion/intrusion . 1. controlling dimension : mm note : 06/04/2008 package outline

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